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256-position, two-time programmable, i 2 c digital potentiometer ad5170 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2009 analog devices, inc. all rights reserved. features 256-position digital potentiometer two-time programmable (ttp) set-and-forget resistance setting allows second-chance permanent programming unlimited adjustments prior to one-time programming (otp) activation otp overwrite allows dynamic adjustments with user- defined preset end-to-end resistance: 2.5 k, 10 k, 50 k, 100 k compact 10-lead msop: 3 mm 4.9 mm package fast settling time: t s = 5 s typical in power-up full read/write of wiper register power-on preset to midscale extra package address decode pins: ad0 and ad1 single supply: 2.7 v to 5.5 v low temperature coefficient: 35 ppm/c low power: i dd = 6 a maximum wide operating temperature: ?40c to +125c evaluation board and software are available software replaces microconverter? in factory programming applications applications systems calibration electronics level setting mechanical trimmers replacement in new designs permanent factory pcb settings transducer adjustment of pressure, temperature, position, chemical, and optical sensors rf amplifier biasing automotive electronics adjustments gain control and offset adjustments functional block diagram v dd gnd sda scl ad0 ad1 w rdac register address decode serial input register b a fuse links 12 8 04104-0-001 figure 1. general description the ad5170 is a 256-position, two-time programmable, digital potentiometer 1 that employs fuse link technology, giving users two opportunities to permanently program the resistance setting. for users who do not need to program the digital potentiometer setting in memory more than once, the otp feature is a cost- effective alternative to eemem. the ad5170 performs the same electronic adjustment function as mechanical potentiometers or variable resistors with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. the ad5170 is programmed using a 2-wire, i 2 c?-compatible digital interface. unlimited adjustments are allowed before permanently setting the resistance value, and there are two opportunities for permanent programming. during otp activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer). unlike traditional otp digital potentiometers, the ad5170 has a unique temporary otp overwrite feature that allows for new adjustments even after the fuse is blown. however, the otp setting is restored during subsequent power-up conditions. this feature allows users to treat these digital potentiometers as volatile poten- tiometers with a programmable preset. for applications that program the ad5170 at the factory, analog devices, inc., offers device programming software that runs on windows nt?, windows? 2000, and windows xp operating systems. this software effectively replaces any external i 2 c con- trollers, thus enhancing the time-to-market of the users systems. 1 the terms digital potentiometer, vr, and rdac are used interchangeably.
ad5170 rev. f | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics: 2.5 k ............................................... 3 ? electrical characteristics: 10 k, 50 k, and 100 k ............. 4 ? timing characteristics: 2.5 k, 10 k, 50 k, and 100 k ... 6 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? typical performance characteristics ............................................. 9 ? test circuits ..................................................................................... 13 ? theory of operation ...................................................................... 14 ? one-time programming (otp) .............................................. 14 ? programming the variable resistor and voltage rheostat operation .................................................................... 14 ? programming the potentiometer divider voltage output operation......................................................... 15 ? esd protection ........................................................................... 16 ? terminal voltage operating range ......................................... 16 ? power-up sequence ................................................................... 16 ? power supply considerations ................................................... 16 ? layout considerations ............................................................... 17 ? controlling the ad5170 ................................................................ 18 ? software programming ............................................................. 18 ? device programming ................................................................. 18 ? i 2 c controller programming .................................................... 20 ? i 2 c-compatible, 2-wire serial bus .......................................... 20 ? level shifting for different voltage operation ...................... 21 ? outline dimensions ....................................................................... 22 ? ordering guide .......................................................................... 22 ? revision history 5/09rev. e to rev. f changes to resistor integral nonlinearity, table 1 ...................... 3 changes to full-scale error, table 1 .............................................. 3 changes to zero-scale error, table 1 ............................................. 3 changes to table 10 ........................................................................ 19 changes to figure 46 ...................................................................... 20 12/08rev. d to rev. e changes to resistor integral nonlinearity, table 1 ...................... 3 changes to otp supply voltage parameter, table 1.................... 3 changes to otp voltage parameter, table 2 ................................ 5 changes to table 5 ............................................................................ 8 changes to one-time programming (otp) section ................ 14 changes to power supply considerations section ..................... 16 change to caption, figure 49 ....................................................... 22 changes to ordering guide .......................................................... 22 7/08rev. c to rev. d changes to power supplies parameter in table 1 and table 2 ... 3 updated fuse blow condition to 400 ms throughout ............... 5 1/08rev. b to rev. c updated format .................................................................. universal changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to table 3 ............................................................................ 6 changes to table 5 ............................................................................ 8 inserted figure 25 ........................................................................... 12 changes to one-time programming (otp) section................ 14 changes to power supply considerations section .................... 16 deleted figure 38 and figure 39 .................................................. 17 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21 5/05rev. a to rev. b changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 5 changes to pin function descriptions ........................................... 9 changes to figure 28 ...................................................................... 14 changes to power supply considerations section .................... 17 changes to i 2 c-compatible 2-wire serial bus section ............ 21 added level shifting for different voltage operation section 23 added figure 48 ............................................................................. 23 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 11/04rev. 0 to rev. a changes to electrical characteristics table 1 ................................ 3 changes to electrical characteristics table 2 ................................ 4 changes to one-time programming ......................................... 12 changes to figure 37, figure 38, and figure 39 ........................ 14 changes to power supply considerations .................................. 14 changes to figure 40 ...................................................................... 15 changes to layout considerations .............................................. 15 11/03revision 0: initial version
ad5170 rev. f | page 3 of 24 specifications electrical characteristics: 2.5 k v dd = 5 v 10% or 3 v 10%, v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 1. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?2 0.1 +2 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ?14 2 +14 lsb nominal resistor tolerance 3 ?r ab t a = 25c ?20 +55 % resistance temperature coefficient (?r ab /r ab )/?t 35 ppm/c r wb (wiper resistance) r wb code = 0x00, v dd = 5 v 160 200 dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl ?1.5 0.1 +1.5 lsb integral nonlinearity 4 inl ?2 0.6 +2 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff ?14 ?5.5 0 lsb zero-scale error v wzse code = 0x00 0 4.5 12 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance a, capacitance b 6 c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w 6 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high (sda and scl) 8 v ih v dd = 5 v 0.7 v dd v dd + 0.5 v input logic low (sda and scl) 8 v il v dd = 5 v ?0.5 +0.3 v dd v input logic high (ad0 and ad1) v ih v dd = 3 v 2.1 v input logic low (ad0 and ad1) v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v otp supply voltage 8 , 9 v dd_otp t a = 25c 5.6 5.7 5.8 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current 8 , 10 , 11 i dd_otp v dd_otp = 5 v, t a = 25c 100 ma power dissipation 12 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 33 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/%
ad5170 rev. f | page 4 of 2 4 parameter symbol conditions min typ 1 max unit dynamic characteristics 13 C3 db bandwidth bw_2.5k code = 0x80 4.8 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 1.25 k, f = 1 khz 3.2 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from the ideal between successive tap positions. parts are guaranteed monoto nic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 5 the a, b, and w resistor terminals have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 the minimum voltage re quirement on the v ih is 0.7 v v dd . for example, v ih minimum = 3.5 v when v dd = 5 v. it is typical for the scl and sda resistors to be pulled up to v dd . however, care must be taken to ensure that the minimum v ih is met when the scl and sda are driven directly from a low voltage logic controller without pull-up resistors. 9 different from operating power supply; power supply for otp is used one time only. 10 different from operating current; su pply current for otp lasts approximat ely 400 ms for use one time only. 11 see figure 26 for the energy plot during otp program. 12 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 13 all dynamic characteristics use v dd = 5 v. electrical characteristics: 10 k, 50 k, and 100 k v dd = 5 v 10% or 3 v 10%, v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 2. parameter symbol conditions min typ 1 max unit dc characteristicsrheostat mode resistor differential nonlinearity 2 r-dnl r wb , v a = no connect ?1 0.1 +1 lsb resistor integral nonlinearity 2 r-inl r wb , v a = no connect ?2.5 0.25 +2.5 lsb nominal resistor tolerance 3 ?r ab t a = 25c ?20 +20 % resistance temperature coefficient (?r ab /r ab )/?t 35 ppm/c r wb (wiper resistance) r wb code = 0x00, v dd = 5 v 160 200 dc characteristicspotentiometer divider mode (specifications apply to all vrs) differential nonlinearity 4 dnl ?1 0.1 +1 lsb integral nonlinearity 4 inl ?1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full-scale error v wfse code = 0xff ?2.5 ?1 0 lsb zero-scale error v wzse code = 0x00 0 1 2.5 lsb resistor terminals voltage range 5 v a , v b , v w gnd v dd v capacitance a, capacitance b 6 c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w 6 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 7 i a_sd v dd = 5.5 v 0.01 1 a common-mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high (sda and scl) 8 v ih v dd = 5 v 0.7 v dd v dd + 0.5 v input logic low (sda and scl) 8 v il v dd = 5 v ?0.5 +0.3 v dd v input logic high (ad0 and ad1) v ih v dd = 3 v 2.1 v input logic low (ad0 and ad1) v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 6 c il 5 pf
ad5170 rev. f | page 5 of 24 parameter symbol conditions min typ 1 max unit power supplies power supply range v dd range 2.7 5.5 v otp supply voltage 8 , 9 v dd_otp 5.6 5.7 5.8 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a otp supply current 8 , 10 , 11 i dd_otp v dd_otp = 5 v, t a = 25c 100 ma power dissipation 12 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 33 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 13 C3 db bandwidth bw r ab = 10 k, code = 0x80 600 khz r ab = 50 k, code = 0x80 100 khz r ab = 100 k, code = 0x80 40 khz total harmonic distortion thd w v a =1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k 0.1 % v w settling time (10 k/50 k/100 k) t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage density e n_wb r wb = 5 k, f = 1 khz 9 nv/hz 1 typical specifications represe nt average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error, r-inl, is the deviatio n from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from the ideal between successive tap positions. parts are guaranteed monoto nic. 3 v ab = v dd , wiper (v w ) = no connect. 4 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 5 the a, b, and w resistor terminals have no limitations on polarity with respect to each other. 6 guaranteed by design and not subject to production test. 7 measured at the a terminal. the a terminal is open circuited in shutdown mode. 8 the minimum voltage re quirement on the v ih is 0.7 v v dd . for example, v ih minimum = 3.5 v when v dd = 5 v. it is typical for the scl and sda resistors to be pulled up to v dd . however, care must be taken to ensure that the minimum v ih is met when the scl and sda are driven directly from a low voltage logic controller without pull- up resistors. 9 different from operating power supply, power supply otp is used one time only. 10 different from operating current, su pply current for otp lasts approximat ely 400 ms for use one time only. 11 see figure 26 for the energy plot during otp program. 12 p diss is calculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 13 all dynamic characteristics use v dd = 5 v.
ad5170 rev. f | page 6 of 24 timing characteristics: 2.5 k, 10 k, 50 k, and 100 k v dd = 5 v 10% or 3 v 10%, v a = v dd ; v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 3. parameter symbol conditions min typ max unit i 2 c interface timing characteristics 1 (specifications apply to all parts) scl clock frequency f scl 400 khz t buf bus free time between stop and start t 1 1.3 s t hd;sta hold time (repeated start) t 2 after this period, the first clock pulse is generated 0.6 s t low low period of scl clock t 3 1.3 s t high high period of scl clock t 4 0.6 s t su;sta setup time for repeated start condition t 5 0.6 s t hd;dat data hold time 2 t 6 0.9 s t su;dat data setup time t 7 100 ns t f fall time of both sda and scl signals t 8 300 ns t r rise time of both sda and scl signals t 9 300 ns t su;sto setup time for stop condition t 10 0.6 s otp program time t 11 400 ms 04104-044 1 see figure 2 for locations of measured values. 2 the maximum t hd;dat must be met only if the device does not stretch the low period (t low ) of the scl signal. timing diagram t 1 ps s sda p t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 scl figure 2. i 2 c interface detailed timing diagram
ad5170 rev. f | page 7 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +7 v v a , v b , v w to gnd v dd terminal current, a to b, a to w, b to w 1 pulsed 20 ma continuous 5 ma digital inputs and output voltage to gnd 0 v to 7 v operating temperature range ?40c to +125c maximum junction temperature (t jmax ) 150c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c thermal resistance 2 ja : 10-lead msop 230c/w 1 maximum terminal current is bound by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 package power dissipation = (t jmax ? t a )/ ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5170 rev. f | page 8 of 24 pin configuration and fu nction descriptions b 1 a 2 ad0 3 g nd 4 w 10 nc 9 ad1 8 sda 7 v dd 5 ad5170 top view (not to scale) 04104-04 8 scl 6 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 b b terminal. gnd v b v dd . 2 a a terminal. gnd v a v dd . 3 ad0 programmable address bit 0 for multiple package decoding. 4 gnd digital ground. 5 v dd positive power supply. specified for operation from 2.7 v to 5.5 v. for otp programming, the v dd supply must be within the 5.6 v to 5.8 v range and capable of driving 100 ma. 6 scl serial clock input. positive edge triggere d. requires a pull-up resistor. if it is driven directly from a logic controller without the pull-up resistor, ensure that v ih minimum is 0.7 v v dd . 7 sda serial data input/output. requires a pull-up resistor. if it is driven directly from a logic controller without the pull-up resistor, ensure that v ih minimum is 0.7 v v dd . 8 ad1 programmable address bit 1 for multiple package decoding. 9 nc no connect. 10 w w terminal. gnd v w v dd .
ad5170 rev. f | page 9 of 24 typical performance characteristics ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheost a t mode inl (lsb) 1.0 1.5 2.0 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04104-005 128 96 32 64 0 160 192 224 256 code (decimal) 04104-002 v dd = 5.5v t a = 25c r ab = 10k ? v dd = 2.7v r ab = 10k ? v dd = 2.7v; t a = ?40c, +25c, +85c, +125c figure 4. r-inl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rheost a t mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04104-003 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v figure 5. r-dnl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode inl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04104-004 r ab = 10k ? v dd = 2.7v t a = ?40c, +25c, +85c, +125c v dd = 5.5v t a = ?40c, +25c, +85c, +125c figure 6. inl vs. code vs. temperature figure 7. dnl vs. code vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 potentiometer mode inl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04104-006 t a = 25c r ab = 10k ? v dd = 5.5v v dd = 2.7v figure 8. inl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04104-007 t a = 25c r ab = 10k ? v dd = 2.7v v dd = 5.5v figure 9. dnl vs. code vs. supply voltages
ad5170 rev. f | page 10 of 24 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheost a t mode inl (lsb) 1.0 1.5 0 0.75 1.50 2.25 3.00 3.75 4.50 zse, zero-scale error (lsb) temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 04104-011 r ab = 10k ? r ab = 10k ? v dd = 2.7v t a = ?40c, +25c, +85c, +125c 128 96 32 64 0 160 192 224 256 08 code (decimal) 04104-0 v dd = 5.5v t a = ?40c, +25c, +85c, +125c v dd = 2.7v, v a = 2.7v v dd = 5.5v, v a = 5.0v figure 10. r-inl vs. code vs. temperature ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rheost a t mode dnl (lsb) 128 96 32 64 0 160 192 224 256 code (decimal) 04104-00 9 v dd = 2.7v, 5.5v; t a = ?40c, +25c, +85c, +125c r ab = 10k ? figure 11. r-dnl vs. code vs. temperature ?2.0 temperature (c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 04104-010 ?1.5 ?1.0 ?0.5 0 0.5 fse, full-scale error (lsb) 1.0 1.5 2.0 v dd = 5.5v, v a = 5.0v r ab = 10k ? v dd = 2.7v, v a = 2.7v figure 12. full-scale error vs. temperature figure 13. zero-scale error vs. temperature i dd , supply current (a) 0.1 1 10 ?40 ?7 26 59 92 125 temperature (c) 04104-012 v dd = 5v v dd = 3v figure 14. i dd , supply current vs. temperature ?20 0 20 40 60 80 100 120 rheost r ab = 10k ? a t mode tempco (ppm/c) 128 96 32 64 0 160 192 224 256 13 v dd = 2.7v t a = ?40c to +85c, ?40c to +125c v dd = 5.5v t a = ?40c to +85c, ?40c to +125c code (decimal) 04104-0 figure 15. rheostat mode tempco r wb /t vs. code
ad5170 rev. f | page 11 of 24 ?30 ?20 ?10 0 10 20 potentiometer mode tempco (ppm/c) 30 40 50 14 128 96 32 64 0 160 192 224 256 code (decimal) 04104-0 r ab = 10k ? v dd = 2.7v t a = ?40c to +85c, ?40c to +125c v dd = 5.5v t a = ?40c to +85c, ?40c to +125c ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 04104-017 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 16. potentiometer mode tempco v wb /t vs. code ?60 ?54 5 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 10k 1m 100k 10m 04104-01 0x80 0x40 0x20 0x10 0x08 0x04 0x010x02 figure 17. gain vs. frequency vs. code, r ab = 2.5 k ?60 ?54 frequency (hz) 1k 100k 10k 1m 04104-016 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 18. gain vs. frequency vs. code, r ab = 10 k figure 19. gain vs. frequency vs. code, r ab = 50 k ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 04104-018 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 20. gain vs. frequency vs. code, r ab = 100 k ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) 9 100k? 60khz 50k? 120khz 10k ? 570khz 2.5k ? 2.2mhz frequency (hz) 10k 1k 100k 1m 10m 04104-01 figure 21. ?3 db bandwidth at code = 0x80
ad5170 rev. f | page 12 of 2 4 i dd , supply current (ma) 1 0.1 10 0.01 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 04104-020 digital input voltage (v) t a = 25c v dd = 2.7v v dd = 5.5v figure 22. i dd , supply current vs. digital input voltage scl v w 04104-021 figure 23. digital feedthrough v w 04104-025 04104-023 v w scl figure 25. large signal settling time figure 24. midscale glitch, code 0x80 to code 0x7f 04104-033 ch1 20.0ma ? m 200ns a ch1 32.4ma 1 t 588.000ns ch1 max 103ma ch1 min ?1.98ma figure 26. otp program energy plot for single fuse
ad5170 rev. f | page 13 of 24 test circuits figure 27 to figure 32 illustrate the test circuits that define the test conditions used in the product specification tables. 0 4104-026 v ms a w b dut v+ v + = v dd 1lsb = v+/2 n figure 27. test circuit for potentiometer divider nonlinearity error (inl, dnl) 04104-027 no connect i w v ms a w b dut figure 28. test circuit for resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) 04104-028 v ms2 v ms1 v w a w b dut i w = v dd /r nominal r w = [v ms1 ? v ms2 ]/i w figure 29. test circuit for wiper resistance 04104-029 v ms % dut ( ) a w b v+ v dd % v ms v dd v dd v a v ms v+ = v dd 10% psrr (db) = 20 log pss (%/%) = figure 30. test circuit for powe r supply sensitivity (pss, psrr) 04104-030 +5v dut ?5v w a 2.5v b v out offset gnd v in ad8610 figure 31. test circuit for gain vs. frequency w b i cm a nc v cm gnd nc nc = no connect v dd dut 041 04-032 figure 32. test circuit for common-mode leakage current
ad5170 rev. f | page 14 of 2 4 04104-022 sda scl a w b theory of operation comparator mux decoder fuses en fuse reg. dac reg. i 2 c interface one-time program/test control block figure 33. detailed fu nctional block diagram the ad5170 is a 256-position, digitally controlled, variable resistor (vr) that employs fuse link technology to achieve memory retention of the resistance setting. an internal power-on preset places the wiper at midscale during power-on. if the otp function is activated, the device powers up at the user-defined permanent setting. one-time programming (otp) prior to otp activation, the ad5170 presets to midscale during initial power-on. after the wiper is set at the desired position, the resistance can be permanently set by programming the t bit high along with the proper coding (see table 9 and table 10 ) and one-time v dd_otp . note that fuse link technology of the ad517x family of digital potentiometers requires that v dd_otp between 5.6 v and 5.8 v blow the fuses to achieve a given nonvolatile setting. on the other hand, v dd can be 2.7 v to 5.5 v during operation. for system supplies that are lower than 5.6 v, an external supply for one-time programming is required. note that the user is allowed only one attempt in blowing the fuses. if the user fails to blow the fuses at the first attempt, the structures of the fuses may have changed such that they can never be blown, regardless of the energy applied at subsequent events. for details, see the power supply considerations section. the device control circuit has two validation bits, e1 and e0, that can be read back to check the programming status (see table 6 ). users should always read back the validation bits to ensure that the fuses are properly blown. after the fuses are blown, all fuse latches are enabled upon subsequent power-on; therefore, the output corresponds to the stored setting. figure 33 shows a detailed functional block diagram. table 6. validation status e1 e0 status 0 0 ready for programming. 1 0 fatal error. some fuses are not blown. do not retry. discard this unit. 1 1 successful. no further programming is possible. programming the variable resistor and voltagerheostat operation the nominal resistance (r ab ) between terminal a and terminal b is available in 2.5 k, 10 k, 50 k, and 100 k. the nominal resistance of the vr has 256 contact points that are accessed by the wiper terminal, plus the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. a w b a w b a w b 0 4104-024 figure 34. rheostat mode configuration assuming that a 10 k part is used, the first connection of the wiper starts at terminal b for data 0x00. because there is a 50 wiper contact resistance, such a connection yields a minimum of 100 (2 50 ) resistance between terminal w and terminal b. the second connection is the first tap point, which corresponds to 139 (r wb = r ab /256 + 2 r w = 39 + 2 50 ) for data 0x01. the third connection is the next tap point, representing 178 (2 39 + 2 50 ) for data 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 (r ab + 2 r w ).
ad5170 rev. f | page 15 of 24 d5 d4 d3 d7 d6 d2 d1 d0 rdac latch and decoder r s r s r s a r s w b sd bit 04104-034 figure 35. equivalent rdac circuit the general equation that determines the digitally programmed output resistance between terminal w and terminal b is w ab wb rr d (d)r += 2 128 (1) where: d is the decimal equivalent of the binary code loaded in the 8-bit rdac register. r ab is the end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. in summary, if r ab = 10 k and terminal a is open-circuited, the output resistance, r wb , is set for the rdac latch codes, as shown in table 7 . table 7. codes and corresponding r wb resistance d dec r wb utput state 255 9961 full scale (r ab ? 1 lsb + r w ) 128 5060 midscale 1 139 1 lsb 0 100 zero scale (wiper contact resistance) note that in the zero-scale condition, a finite wiper resistance of 100 is present. care should be taken to limit the current flow between terminal w and terminal b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact can occur. similar to the mechanical potentiometer, the resistance of the rdac between the wiper (terminal w) and terminal a also produces a digitally controlled, complementary resistance, r wa . when these terminals are used, terminal b can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is w ab wa rr d (d)r += 2 128 C256 (2) for r ab = 10 k and terminal b open circuited, table 8 shows some examples of the output resistance (r wa ) vs. the rdac latch codes. table 8. codes and corresponding r wa resistance d dec r wa utput state 255 139 full scale 128 5060 midscale 1 9961 1 lsb 0 10,060 zero scale typical device-to-device matching is process-lot dependent and can vary by up to 30%. because the resistance element is processed using thin film technology, the change in r ab with temperature has a very low 35 ppm/c temperature coefficient. programming the potentiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper to b and wiper to a proportional to the input voltage at a to b. unlike the polarity of v dd to gnd, which must be positive, voltage across a to b, w to a, and w to b can be at either polarity. a w b v i v o 0 4104-035 figure 36. potentiometer mode configuration if ignoring the effect of the wiper resistance for approximation, connecting terminal a to 5 v and terminal b to ground pro- duces an output voltage at the wiper to b starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across terminal a and terminal b divided by the 256 positions of the potentiometer divider. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b is b a w v d v d dv 256 256 256 )( ? += (3) for a more accurate calculation, which includes the effect of wiper resistance, v w , the following equation can be used: b ab wa a ab wb w v r dr v r dr dv )( )( )( + = (4) operation of the digital potentiometer in divider mode results in a more accurate operation over temperature. unlike rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, r wa and r wb , and not the absolute values. therefore, the temperature drift reduces to 15 ppm/c.
ad5170 rev. f | page 16 of 24 esd protection all digital inputs, sda, scl, ad0, and ad1, are protected with a series input resistor and parallel zener esd structures, as shown in figure 37 and figure 38 . logic 340 ? gnd 04104-037 figure 37. esd protection of digital pins a, b, w gnd 04104-038 figure 38. esd protection of resistor terminals terminal voltage operating range the ad5170 v dd -to-gnd power supply defines the boundary conditions for proper 3-terminal digital potentiometer opera- tion. supply signals present on terminal a, terminal b, and terminal w that exceed v dd or gnd are clamped by the internal forward-biased diodes (see figure 39 ). gnd b a w v dd 04104-039 figure 39. maximum terminal voltages set by v dd and gnd power-up sequence because the esd protection diodes limit the voltage compliance at te r m i n a l a , te r m i n a l b, a nd te r m i n a l w, it i s i mp or t ant to power v dd /gnd before applying any voltage to terminal a, te r m i n a l b, a nd te r m i n a l w ( s e e figure 39 ). otherwise, the diode is forward-biased such that v dd is powered unintentionally and may affect the rest of the users circuit. the ideal power-up sequence is gnd, v dd , the digital inputs, and then v a /v b /v w . the relative order of powering v a , v b , v w , and the digital inputs is not important as long as they are powered up after gnd/v dd . power supply considerations to minimize the package pin count, both the one-time pro- gramming and normal operating voltage supplies share the same v dd terminal of the ad5170. the ad5170 employs fuse link technology that requires 5.6 v to 5.8 v for blowing the internal fuses to achieve a given setting, but normal v dd can be anywhere between 2.7 v and 5.5 v after the fuse programming process. as a result, dual voltage supplies and isolation are needed if system v dd is lower than the required v dd_otp . the fuse program- ming supply (either an on-board regulator or rack-mount power supply) must be rated at 5.6 v to 5.8 v and be able to provide a 100 ma current for 400 ms for successful otp. when the fuse programming is complete, the v dd_otp supply must be removed to allow normal operation at 2.7 v to 5.5 v, and the device consumes current in the a range. v dd 2.7v 5.7v p1 p1 = p2 = fdv302p, nds0610 r1 10k? p2 c1 10f c2 0.1f a pply for otp only ad5170 0 4104-0-51 figure 40. isolate 5.7 v otp supply from 2.7 v normal operating supply for example, for those who operate their systems at 2.7 v, use of the bidirectional, low threshold, p-channel mosfets is recom- mended for the isolation of the supply. as shown in figure 40 , this assumes that the 2.7 v system voltage is applied first, and the p1 and p2 gates are pulled to ground, thus turning on p1 and, subsequently, p2. as a result, v dd of the ad5170 approaches 2.7 v. when the ad5170 setting is found, the factory tester applies the v dd_otp to both the v dd and the mosfets gates, turning off p1 and p2. the otp command is executed at this time to program the ad5170 while the 2.7 v source is protected. when the fuse pro- gramming is complete, the tester withdraws the v dd_otp and the setting for the ad5170 is permanently fixed. the ad5170 achieves the otp function by blowing internal fuses. users should always apply the 5.6 v to 5.8 v one-time- program voltage requirement at the first fuse programming attempt. failure to comply with this requirement can lead to a change in the fuse structures, rendering programming inoperable. care should be taken when scl and sda are driven from a low voltage logic controller. users must ensure that the logic high level is between 0.7 v v dd and v dd + 0.5 v. refer to the level shifting for different voltage operation section. poor pcb layout introduces parasitics that can affect the fuse programming. therefore, it is recommended to add a 10 f tantalum capacitor in parallel with a 1 nf ceramic capacitor as close as possible to the v dd pin. the type and value chosen for both capacitors are important. this combination of capacitor values provides both a fast response and larger supply current handling with minimum supply droop during transients. as a result, these capacitors increase the otp programming success by not inhibiting the proper energy needed to blow the internal fuses. additionally, c1 minimizes transient disturbance and low frequency ripple, and c2 reduces high frequency noise during normal operation.
ad5170 rev. f | page 17 of 24 layout considerations it is good practice to employ compact, minimum lead length, layout design. the leads to the inputs should be as direct as possible, with a minimum conductor length. ground paths should have low resistance and low inductance. v dd v dd c2 1nf c1 10f + ad5170 note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. gnd 04104-040 figure 41. power supply bypassing
ad5170 rev. f | page 18 of 24 04104-041 controlling the ad5170 there are two ways of controlling the ad5170. users can program the device with either computer software or external i 2 c controllers. figure 42. ad5170 computer software interface software programming due to the advantages of the one-time programmable feature, consider programming the device in the factory before shipping the final product to the end users. analog devices offers device programming software that can be implemented in the factory on pcs running windows 95 or later. as a result, external con- trollers are not required, significantly reducing development time. the program is an executable file that does not require knowledge of programming languages or programming skills, and it is easy to set up and to use. figure 42 shows the software interface. the software can be downloaded from the ad5170 product page. write the ad5170 starts at midscale after power-up prior to otp programming. to increment or decrement the resistance, move the scroll bars on the left. to write any specific value, use the bit pattern in the upper screen and click run . the format of writing data to the device is shown in table 9 . once the desired setting is found, click program permanent: first fuse link to blow the internal fuse links. read to read the validation bits and data from the device, click read . the format of the read bits is shown in table 1 0 . device programming to apply the device programming software in the factory, modify a parallel port cable and configure pin 2, pin 3, pin 15, and pin 25 for sda_write, scl, sda_read, and dgnd, respectively, for the control signals (see figure 43 ). also, lay out the pcb of the ad5170 with scl and sda pads, as shown in figure 44 , such that pogo pins can be inserted for factory programming. 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 scl r3 100? r2 100 ? r1 100? sda read write 0 4104-042 figure 43. parallel port connection (pin 2 = sda_write, pin 3 = scl, pin 15 = sda_read, and pin 25 = dgnd) a d5170 b a ad0 gnd vdd w nc ad1 sda scl 04104-043 figure 44. recommended ad5170 pcb layout
ad5170 rev. f | page 19 of 24 table 9. write mode s 0 1 0 1 1 ad1 ad0 w a 2t sd t 0 ow x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte table 10. read mode s 0 1 0 1 1 ad1 ad0 r a d7 d6 d5 d4 d3 d2 d1 d0 a e1 e0 x x x x x x a p slave address byte data byte validation byte table 11. sda bit definitions and descriptions bit description s start condition. p stop condition. a acknowledge. ad0, ad1 package pin-programmable address bits. x dont care. w write. r read. 2t second fuse link array for two-time programming. logic 0 corresponds to first trim. logic 1 corresponds to second trim. note that blowing trim 2 before trim 1 effectiv ely disables trim 1 and, in turn, allows only one-time programming. sd shutdown connects wiper to terminal b and open circuits terminal a. it does not change the contents of the wiper register. t otp programming bit. logic 1 permanently programs the wiper. ow overwrite the fuse setting and program the digital potentiom eter to a different setting. note that upon power-up, the digital potentiometer presets to either midscale or fuse setting, depending on whether the fuse link is blown. d7, d6, d5, d4, d3, d2, d1, and d0 data bits. e1, e0 otp validation bits: 0, 0 = ready to program. 1, 0 = fatal error. some fuses are not blown. do not retry. discard this unit. 1, 1 = programmed successfully. no further adjustments are possible.
ad5170 rev. f | page 20 of 2 4 045 scl i 2 c controller programming write bit patterns 04104- s tart by master frame 1 s lave address byte frame 2 instruction byte frame 3 data byte stop by master sda 01 1 0 1 1 ad1 ad0 ack by ad5170 r/w a0 sd 0 ow xxx 19 d7 d6 d5 d4 d3 ack by ad5170 19 t 9 d2 d1 d0 ack by ad5170 figure 45. writing data to the rdac register read bit pattern 04104-046 scl s tart by master sda 01 1 fram e 1 slave address byte 0 1 1 ad1 ad0 frame 2 data byte ack by ad5170 r/w d7 d6 d4 d3 d2 d1 d0 19 e1 e0 x x x ack by master frame 3 validation byte 19 d5 stop by master 9 xxx no ack by master figure 46. reading data from the rdac register the third msb, t, is the otp programming bit. a logic high blows the polyfuses and programs the resistor setting perma- nently. for example, if the user wants to blow the first array of fuses, the instruction byte is 00100xxx. to blow the second array of fuses, the instruction byte is 10100xxx. a logic low of the t bit simply allows the device to act as a typical volatile digital potentiometer. i 2 c-compatible, 2-wire serial bus the following section describes how the 2-wire, i 2 c serial bus protocol operates (see figure 45 and figure 46 ). the master initiates a data transfer by establishing a start con- dition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 45 ). the following byte is the slave address byte, which consists of the slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). ad0 and ad1 are configurable address bits that allow up to four devices on one bus (see ). table 9 the fourth msb must always be logic 0. the fifth msb, ow, is an overwrite bit. when raised to a logic high, ow allows the rdac setting to be changed even after the internal fuses are blown. however, when ow is returned to logic 0, the position of the rdac returns to the setting prior to the overwrite. because ow is not static, if the device is powered off and on, the rdac presets to midscale or to the setting at which the fuses were blown, depending on whether the fuses are permanently set. the slave address corresponding to the transmitted address bits responds by pulling the sda line low during the ninth clock pulse (this is called the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register. if the r/ w bit is high, the master reads from the slave device. if the r/ w bit is low, the master writes to the slave device. the remainder of the bits in the instruction byte are dont care bits (see figure 45 ). in write mode, the second byte is the instruction byte. the first msb of the instruction byte, 2t, is the second trim enable bit. a logic low selects the first array of the fuses, and a logic high selects the second array of the fuses. this means that after blowing the fuses with trim 1, the user still has another chance to blow them again with trim 2. note that using trim 2 before trim 1 effectively disables trim 1 and, in turn, allows only one-time programming. after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 2 ). in read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference from write mode, with eight data bits followed by an acknowledge bit). similarly, transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 46 ). the second msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a and shorts the wiper to terminal b. this operation yields almost 0 in rheostat mode or 0 v in potentiometer mode. note that the shutdown operation does not disturb the contents of the register. when brought out of shutdown, the previous setting is applied to the rdac. in addition, new settings can be programmed during shutdown. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. following the data byte, the validation byte contains two valida- tion bits, e0 and e1. these bits signify the status of the one-time programming (see figure 46 ).
ad5170 rev. f | page 21 sda sda ad1 ad0 master scl scl ad5170 sda ad1 ad0 scl ad5170 sda ad1 ad0 scl ad5170 sda 5v r p r p 5v 5v 5v ad1 ad0 scl ad5170 of 24 after all the data bits are read or written, a stop condition is established by the master. a stop condition is defined as a low- to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10th clock pulse to establish a stop condition (see figure 45 ). in read mode, the master issues a no acknowledge for the 9th clock pulse (that is, the sda line remains high). the master brings the sda line low before the 10th clock pulse and then brings the sda line high to establish a stop condition (see figure 46 ). 04104-047 a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. for example, after the rdac has acknowledged its slave address and instruction bytes in write mode, the rdac output updates on each successive byte. if different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed. multiple devices on one bus figure 47 shows four ad5170s on the same serial bus. each has a different slave address because the states of their ad0 and ad1 pins are different, which allows each device on the bus to be written to or read from independently. the master device output bus line drivers are open-drain pull-downs in a fully i 2 c-compatible interface. figure 47. multiple ad5170s on one i 2 c bus level shifting for different voltage operation if the scl and sda signals come from a low voltage logic con- troller and are below the minimum v ih level (0.7 v v dd ), level shift the signals for read/write communications between the ad5170 and the controller. figure 48 shows one of the implemen- tations. for example, when sda1 is at 2.5 v, m1 turns off and sda2 becomes 5 v. when the sda1 is at 0 v, m1 turns on and the sda2 approaches 0 v. as a result, proper level shifting is established. m1 and m2 should be low threshold, n-channel power mosfets, such as the fdv301n. 410 0 4-052 2.5v controller 2.7v to 5.5v ad5170 rp rp rp rp v dd1 = 2.5 v v dd2 = 5 v g g s d m1 s d m2 s da1 s cl1 sda2 scl2 figure 48. level shifting for different voltage operation
ad5170 rev. f | page 22 of 2 4 compliant to jedec standards mo-187-ba outline dimensions 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.10 3.00 2.90 pin 1 5.15 4.90 4.65 3.10 3.00 2.90 coplanarity 0.10 figure 49. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model r ab (k) temperature range package description package option branding ad5170brm2.5 2.5 C40c to +125c 10-lead msop rm-10 dd2 ad5170brm2.5-rl7 2.5 C40c to +125c 10-lead msop rm-10 dd2 ad5170brmz2.5 1 2.5 C40c to +125c 10-lead msop rm-10 dd7 ad5170brm10 10 C40c to +125c 10-lead msop rm-10 dd3 ad5170brm10-rl7 10 C40c to +125c 10-lead msop rm-10 dd3 ad5170brmz10 1 10 C40c to +125c 10-lead msop rm-10 dd4 AD5170BRMZ10-RL7 1 10 C40c to +125c 10-lead msop rm-10 dd4 ad5170brm50 50 C40c to +125c 10-lead msop rm-10 dd0 ad5170brm50-rl7 50 C40c to +125c 10-lead msop rm-10 dd0 ad5170brmz50 1 50 C40c to +125c 10-lead msop rm-10 dd6 ad5170brm100 100 C40c to +125c 10-lead msop rm-10 dd1 ad5170brm100-rl7 100 C40c to +125c 10-lead msop rm-10 dd1 ad5170brmz100 1 100 C40c to +125c 10-lead msop rm-10 dd5 ad5170eval 2 evaluation board 1 z = rohs compliant part. 2 the evaluation board is shipped with the 10 k r ab resistor option; however, the board is compatible with all available resistor value options.
ad5170 rev. f | page 23 of 2 4 notes
ad5170 rev. f | page 24 of 24 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2003C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04104-0-5/09(f)

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